This invention relates to a serial arithmetic processor which is arranged to perform complex arithmetic functions. The invention more particularly relates to a serial arithmetic processor for adaptive differential pulse code modulation (ADPCM) applications wherein the processor is arranged to efficiently and quickly perform arithmetically complex functions.
Digital encoding of voice channels has long been the standard in the telephonic arts. To provide quality transmission and reproduction, techniques such as pulse code modulation (PCM) at sixty-four kilobits/sec, and differential pulse code modulation (DPCM) have been employed. More recently, the ADPCM technique has been shown to provide advantages in speech encoding by permitting acceptable quality at rates of 32 kilobits/second or less. Indeed, many variations of ADPCM have been proposed as is evidenced by Benvenuto, Nevio, et al., "The 32 KB/S ADPCM Coding Standard" AT&T Technical Journal, Vol 65, Issue 5, October 1986 pp 12-22.
In light of the progress made in the area of ADPCM, the CCITT has adopted a recommendation (CCITT Rec. G.721 which is hereby incorporated by reference herein) providing a specified algorithm for the 32 kilobit/second transcoder. Presently, ANSI is considering providing ADPCM standards as may be seen by Draft Standard Tl/LB 81, July 23, 1986, which is also hereby incorporated by reference herein.
Regardless of the particular standards or algorithm finally adopted, it is evident that various arithmetic functions must be performed on the voice signals are to provide a high quality ADPCM signal. Thus, a LOG function which converts a sixteen bit unsigned magnitude value into the logarithmic domain; a FLOAT function which converts a sixteen bit signed magnitude value into floating point representation; an ANTILOG function which converts a four bit exponent, seven bit mantissa logarithm into the linear domain; a MULTIPLICATION function for performing fourteen bit by eight bit signed magnitude multiplication; and a FLOATlNG POINT MULTIPLICATION function for performing a four exponent, six mantissa by four exponent, six mantissa floating point multiplication combined with an output conversion from floating point to signed magnitude; are all required by all ADPCM algorithms (See Sections 6.4.2.2, 6.4.2.3, 6.4.2.4, and 6.4.2.6 of Draft Standard T1/LB 81).
Those skilled in the art are well aware that the above-listed arithmetic functions are not found in the instruction sets of the digital signal processing microchips presently available. Thus, in implementing the ADPCM algorithm, it has become standard to provide software routines to perform the arithmetically complex functions. However, such software programs have proved burdensome, both in their requirement for large microcode storage, and the execution time required for accomplishing the program.